Описание продукта
The NB3N853501E is a low skew 3.3 V supply 2:1:4 clock distribution fanout buffer. An Input MUX selects one of two LVCMOS/LVTTL CLK lines by the CLK_SEL pin (HIGH for CLK1, LOW for CLK0) using LVCMOS/LVTTL levels. A CLK_EN pin can enable or disable the outputs synchronously to eliminate runt pulses using LVCMOS/LVTTL levels (HIGH to enable outputs, LOW to disable output).
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Отличительные черты |
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Benefits |
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Four differential LVPECL Outputs
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Multiple copies of the Clock
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Operating range: VCC = 3.3 5% V( 3.135 to 3.465 V)
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Ensures operation in the majority of designs
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Two Selectable LVCMOS/LVTTL CLOCK Inputs
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Up to 266 MHz Clock Operation
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Output to Output Skew: 30 ps
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Device to Device Skew 250 ps (Max.)
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Propagation Delay 1.9 ns (Max.)
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Additive Phase Jitter, RMS: 0.023 ps (Typ)
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Industrial Temp. Range (40C to 85C)
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Применения |
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End Products |
- Teleconmmunications
- Networking
- Computing Systems
- SONET/SDH
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- LAN/WAN
- Enterprise Servers
- ATE
- Test and Measurement
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