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NB6L11: Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL

Overview
Specifications
Datasheet: Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2
Rev. 9 (322.0kB)
»Показать данные по надёжности
»Показать химический состав
»Уведомление об обновлениях схем (2)
GreenPoint® Design Tool
Product Overview
Описание продукта
The NB6L11 is an enhanced differential 1:2 clock or data fan-out buffer/translator. The device has the same pin-out and is functionally equivalent to the LVEL11, EP11 and LVEP11 devices. Moreover, the device is optiminzed for the systems that require LOW skew, LOW jitter and LOW power consumtion.
Differential input can be configured to accept single-ended signal by applying an external reference voltage to unused complementary input pin. Input accept LVNECL, LVPECL, LVTTL, LVCMOS, CML or LVDS. The outputs are 800mV ECL signals.
Отличительные черты
 
  • Input Clock Frequency 6 GHz
  • Input Data Rate 6 Gb/s
  • Low 14 mA Typical Power Supply Current
  • 150 ps Typical Proagation Delay
  • 5 ps Typical Witin Device Skew
  • 75 ps Typical Rise/Fall Times
  • PECL Mode Operating Range: VCC = 2.375 V to 3.465 V with VEE = 0 V
  • NECL Mode Operating Range: VCC = 0 V with VEE = -2.375 V to -3.465 V
  • Open Input Default State
  • Q Outputs will default LOW with Inputs Open or at VEE
Применения
  • Backplane Clock distribution
  • Signal Translation Between LVDS, CML, LVTTL or LVCMOS to LVPECL
Технические информацие
Статьи по применению (15) Спецификацие (1)
Модели - Симуляция (1) Типы корпусов (2)
Наличие и образцы
Продукт
Состояние
Compliance
Описание
Корпус
MSL*
Контейнер
Бюджетная цена единицы
Тип
Размеры
Тип
Кол.
NB6L11DG Active
Pb-free
Halide free
Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL SOIC-8 751-07 1 Tube 98 Contact Sales Office
NB6L11DR2G Active
Pb-free
Halide free
Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL SOIC-8 751-07 1 Tape and Reel 2500 Contact Sales Office
NB6L11DTG Active
Pb-free
Halide free
Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL TSSOP-8 948R-02 3 Tube 100 Contact Sales Office
NB6L11DTR2G Active
Pb-free
Halide free
Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL TSSOP-8 948R-02 3 Tape and Reel 2500 Contact Sales Office
* Уровень чувствительности компонента к влажности
Market Leadtime (weeks) : 2 to 4
Arrow   (Sat Jul 11 08:05:16 MST 2015) : 916
Avnet   (2015-07-09) : <100
Chip1Stop   (2015-07-09) : <1K
Digikey   (2015-07-09) : <100
FutureElectronics   (2015-07-09) : <100
Mouser   (2015-07-09) : <100
ON Semiconductor   (2015-07-08) : 10,094
PandS   (2015-07-09) : <100
Market Leadtime (weeks) : 2 to 4
Market Leadtime (weeks) : 2 to 4
Arrow   (Sat Jul 11 08:05:16 MST 2015) : 935
Avnet   (2015-07-09) : >1K
Chip1Stop   (2015-07-09) : <1K
Digikey   (2015-07-09) : <1K
FutureElectronics   (2015-07-09) : >1K
Mouser   (2015-07-09) : <1K
ON Semiconductor   (2015-07-08) : 8,100
PandS   (2015-07-09) : <100
Market Leadtime (weeks) : 4 to 8
Datasheet: Clock or Data Fanout Buffer / Translator, 2.5 V/3.3 V Multilevel Input to Differential LVPECL/LVNECL 1:2
Rev. 9 (322.0kB)
»Показать данные по надёжности
»Показать химический состав
»Уведомление об обновлениях схем (2)
GreenPoint® Design Tool
Product Overview

Product Compliance Status Description Type Channels Input / Output Ratio Input Level Output Level VCC Typ (V) tJitterRMS Typ (ps) tskew(o-o) Max (ps) tpd Typ (ns) tR & tF Max (ps) fmaxClock Typ (MHz) fmaxData Typ (Mbps) Package Type
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL   Buffer   1   1:2 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2   15   0.15   120   6000   6000   SOIC-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL   Buffer   1   1:2 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2   15   0.15   120   6000   6000   SOIC-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL   Buffer   1   1:2 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2   15   0.15   120   6000   6000   TSSOP-8 
 Pb-free 
 Halide free 
 Active     Clock / Data Fanout Buffer / Translator, 2.5 V / 3.3 V Multilevel Input to 1:2 Differential LVPECL / LVNECL   Buffer   1   1:2 
 CML 
 CMOS 
 ECL 
 LVDS 
 TTL 
 ECL 
 2.5 
 3.3 
 0.2   15   0.15   120   6000   6000   TSSOP-8 
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